1. Field of the Invention
This invention relates generally to high speed transceivers. More particularly, it relates to circuits for calibrating termination resistances of high speed transceivers.
2. Description of the Prior Art
Preventing signal reflections on transmission lines is an important issue when designing high speed transceivers. To achieve impedance matching and reduce signal reflections, it is necessary to set the output/input impedances of a transceiver substantially equal to the characteristic impedance of the transmission line connected to the transceiver. More specifically, the output impedance of the transceiver must be equal to the characteristic impedance of the transmission line when the transceiver operates as a transmitter; the termination impedance of the transceiver must be equal to the characteristic impedance of the transmission line when the transceiver operates as a receiver.
In IC chips, almost all resistances consisting of transistors or resistors vary with processes, operating voltages, and temperatures either slightly or seriously. When the output/input impedances of a transceiver have variations due to aforementioned factors, impedance mismatches occur. For this reason, calibrations for on-die impedances are needed.
Please refer to FIG. 1, which illustrates a calibration circuit proposed in the patent U.S. Pat. No. 6,157,206. In this case, a portion of an integrated circuit 100 is shown. A reference termination device 106 is coupled to a node 110. A resistor 120 is coupled, between node 110 and ground. The resistor 120 is typically a precision resistor (e.g., +/−1%) external to the integrated circuit 100. The reference termination device 106 is configured in series with the resistor 120 to form a voltage divider. A comparator 104 has two input terminals and an output terminal. A first input terminal of the comparator 104 is coupled to node 110, and a second input terminal of the comparator 104 is coupled to a reference voltage source (VREF). In this way, the voltage at node 110 is compared to VREF, which can be substantially set as one half a power supply voltage of the integrated circuit 100. A controller 102 is coupled to the output terminal of comparator 104. Based on the output of the comparator 104, the controller 102 adjusts the reference termination device 106. If the output of the comparator 104 indicates that the voltage at node 110 is higher than VREF, then the controller 102 generates an output that causes the impedance of reference termination device 106 to increase. On the contrary, if the output of the comparator 104 indicates that the voltage at node 110 is lower than VREF, then the controller 102 generates an output that causes the impedance of reference termination device 106 to decrease. By this feedback mechanism, the reference termination device 106 is adjusted to substantially match the external resistor 120.
A controlled termination device 108 is nominally the same as the reference termination device 106 and functions as the termination resistance of an input buffer 112. After the aforementioned feedback loop is stable, the control signal provided from the controller 102 to the reference termination device 106 can be transmitted to the controlled termination device 108. Since the two termination devices 106 and 108 are nominally the same, the controlled termination device 108 also nearly matches the external resistor 120 after being adjusted with the control signal. The controlled termination device 108 is accordingly calibrated. Typically, this calibration process is continuous and transparent to normal chip operation, for example, the operation of the input buffer 112.
The calibration process illustrated in FIG. 1 can also be used to calibrate an output driving impedance consisting of both pull-up transistors and pull-down transistors. Since pull-up and pull-down transistors generally have different conductance and are sized differently, they require two different sets of calibration signals: one for the pull-up transistors and the other for the pull-down transistors.
Furthermore, every section on a chip may require different impedance. Hence, two external resistors and two calibration pins are needed for each section that requires specific impedance. For example, one chip including a transmitter and a receiver needs four calibration pins and four external resistors according to the calibration process illustrated in FIG. 1. In prior arts, for an IC chip that has plural transceivers and/or that must be automatically calibrated against process, voltage and temperature variations, a large number of pins and silicon area are consumed to meet good signal quality. This increases the cost of the chip and the assembly cost of any board on which the chip is used.
Obviously, there is a need in the art for a way to reduce the number of calibration pins and external resistors required. There is also a need to reduce consumed silicon area for calibrating output/input impedances of transceivers while sustaining good high-speed signal quality.